CODEWITHSUNDEEP
mipscpu-architecture
allen
allen

Reputation: 69

Clock cycle in pipelining and single-clock cycle implementation

There are two mechanisms to execute instructions.

  1. Single clock cycle implementation
  2. pipelining.

In MIPS architecture(from the book Computer organization and design), instruction has 5 stages.

So, in single clock cycle implementation, which means during one clock cycle, 5 stages are executed for one instruction.

For example, load instruction(it has 5 stages) is executed in one clock cycle. So other instructions can be executed after this one clock cycle. Let's assume that one clock cycle is 10 secs.

And now, in pipelining, multiple instructions can be overlapped. I'm confused from this concept comparing to one clock cycle's time in above example.

enter image description here

In here to Execute 5 instructions, it needs 9 clock cycles. It means to execute 5 instructions, it needs 90 secs. But in single clock cycle implementation, it just needs 50 secs to execute 5 instructions. Pipelining needs more clock cycles.(Not good) Am I thinking wrong?? or Am I missing something??

And here, So, to execute first instruction lw $10, 20($1), it needs 50 secs??

Upvotes: 1

Views: 11299

Answers (1)

Isuru H
Isuru H

Reputation: 1221

I think the major misconception you are having is that you consider a duration of a clock cycle in both designs to be the same, which is not. Lets denote a clock cycle in single cycle design as X and a clock cycle in pipeline design as Y. In a single cycle design 5 instructions will take 5X cycles and in a pipeline design this will take 9Y cycles.

Now we need to find a relationship between X and Y. Now think of a case where you have only single instruction to execute. In a single cycle design this will take X cycles and in a pipeline design this will take 5Y. If both are clocked at the same rate, X should be equal to 5Y.

Now lets do a bit of substitution maths :-)

Single cycle - 5X

Pipeline - 9Y

Substituting X = 5Y

Single cycle - 25Y

Pipeline - 9Y

There you go. Single cycle design is 2.7X slower than a multi cycle design.

Upvotes: 3

Related Questions