CODEWITHSUNDEEP
makefile
Intelligent Shade of Blue
Intelligent Shade of Blue

Reputation: 6449

Makefile: computed variable name

In the following example Makefile:

EXTENS := .c .C .cc .c++ .cpp .cxx
SOURCES := 1.c 2.C 3.cc 4.c++ 5.cpp 6.cxx
OBJECTS := $(SOURCES)

REPLACE_EXTENS = $(foreach f,$(EXTENS),$(eval $(1) := $(patsubst %$(f),%.o,$($(1)))))
$(call REPLACE_EXTENS, OBJECTS)

all:
    @echo $(SOURCES)
    @echo $(OBJECTS)

I expect the line @echo $(OBJECTS) to output:

1.o 2.o 3.o 4.o 5.o 6.o

However it outputs nothing. What I am doing wrong and what would be the correct way to do it?

Upvotes: 0

Views: 186

Answers (2)

MadScientist
MadScientist

Reputation: 101081

The right way to to do this is to throw out the EXTENS and REPLACE_EXTENS call completely, and write:

SOURCES := 1.c 2.C 3.cc 4.c++ 5.cpp 6.cxx
OBJECTS := $(addsuffix .o,$(basename $(SOURCES))

all:
        @echo $(SOURCES)
        @echo $(OBJECTS)

Upvotes: 1

BrightFlow
BrightFlow

Reputation: 1294

Change $(call REPLACE_EXTENS, OBJECTS) into $(call REPLACE_EXTENS,OBJECTS). No whitespace between arguments for call.

Upvotes: 1

Related Questions