CODEWITHSUNDEEP
vhdl
Jack Hamel
Jack Hamel

Reputation: 11

INOUT port signal is undefined when used as input and output

I have a port signal defined to be and INOUT signal. I set the port to be the output of a D latch and the output is undefined under abnormal circumstances. When I do not run the output of the D latch through another module, all works fine. I need to take the output signal, however, from the d latch and use it as an input to a different module. When this is done, the output from the D latch is ALWAYS undefined. Below is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_level is
    Port ( a_raw : in  STD_LOGIC_VECTOR (3 downto 0);
           b_raw : in  STD_LOGIC_VECTOR (3 downto 0);
              a_latched : inout STD_LOGIC_VECTOR (3 downto 0);
              b_latched : inout STD_LOGIC_VECTOR (3 downto 0);
              reset : in  STD_LOGIC;
              load : in STD_LOGIC;
              s : in STD_LOGIC_VECTOR (3 downto 0);
              out0 : inout STD_LOGIC_VECTOR (3 downto 0);
              out1 : inout STD_LOGIC_VECTOR (3 downto 0);
              out2 : inout STD_LOGIC_VECTOR (3 downto 0);
              out3 : inout STD_LOGIC_VECTOR (3 downto 0);
              out4 : inout STD_LOGIC_VECTOR (3 downto 0);
              out5 : inout STD_LOGIC_VECTOR (3 downto 0);
              flag : inout STD_LOGIC_VECTOR (4 downto 0);
              result : inout STD_LOGIC_VECTOR (3 downto 0));

signal numone : STD_LOGIC_VECTOR (3 downto 0) := "0001";
signal test : STD_LOGIC_VECTOR (3 downto 0) := a_latched;
end top_level;

architecture Structure of top_level is
component fulladdsub
    Port (
    x : inout STD_LOGIC_VECTOR (3 downto 0);
    y : inout STD_LOGIC_VECTOR (3 downto 0);
    cin : in STD_LOGIC;
    sum : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component D_Latch
    Port (
    D : in STD_LOGIC_VECTOR (3 downto 0);
    EN : in STD_LOGIC;
    Q : inout STD_LOGIC_VECTOR (3 downto 0));
end component;  

begin

stage0: D_Latch port map(D=>a_raw, EN=>load, Q=>a_latched);                    -- allows load to stop A,B from changing
stage1: D_Latch port map(D=>b_raw, EN=>load, Q=>b_latched);
--stage2: fulladdsub port map(x=>a_latched, y=>b_latched, cin=>'0', sum=>out0);  -- A+B
--stage3: fulladdsub port map(x=>a_latched, y=>b_latched, cin=>'1', sum=>out1);  -- A-B
stage2: fulladdsub port map(x=>a_latched, y=>numone, cin=>'0', sum=>out2);       -- A+1
--stage5: fulladdsub port map(x=>a_latched, y=>numone, cin=>'1', sum=>out3);        -- A-1
--stage6: fulladdsub port map(x=>b_latched, y=>numone, cin=>'0', sum=>out4);     -- B+1
--stage7: fulladdsub port map(x=>b_latched, y=>numone, cin=>'1', sum=>out5);     -- B-1


end Structure;

b_latched and a_latched are the ports in question here. When I simulate my code as is, a_latched is always undefined (it is used in stage2) and b_latched is defined when it should be. Can anyone help me solve this issue?

Upvotes: 1

Views: 1780

Answers (1)

QuantumRipple
QuantumRipple

Reputation: 1159

When you use an inout, your architecture needs to explicitly drive it to 'Z' when you are trying to use it as an input. Likewise the containing architecture (usually only a testbench for inouts) needs to set its driver to 'Z' when it wants to read the output.

I can't determine exactly what your problem is, because there isn't enough detail in your question; it is missing the implementations of D_Latch and whatever the "another module" is that you are having issues with.

Also bear in mind that if this is for an FPGA target, you should only use inout for top level ports that connect to pins on your FPGA. That is typically the only section of the FPGA that has tri-state buffers (what inout represents in hardware).

If D_Latch is actually written as a latch, then the output will be undefined if you have never asserted the EN, as that's what a latch is supposed to do.

Upvotes: 1

Related Questions