CODEWITHSUNDEEP
vhdlxilinxxilinx-ise
EquipDev
EquipDev

Reputation: 5931

How to use sequential statements (e.g. process) to make constant value but without wait?

For the sake of consistency and ease of maintenance, I would like to make some constants using sequential statements, e.g. in process.

I have defined a range using:

subtype FIELD is natural range 3 downto 0;

A process that makes the value could then look like:

process is
begin
    reg <= (others => '0');
    reg(FIELD) <= (others => '1');
    wait;  -- Error in Xilinx ISE
end process;

However, the wait is not accepted by Xilinx ISE synthesis tool.

One way is of course to use a non-used signal in a process list, like a clock, but that is a kind of ugly.

The concurrent style would be like:

reg <= (FIELD => (others => '1'), others => '0');

But FIELD can't be used like that in VHDL.

Is there a way to make constants using sequential statements, but where the wait is not required in a process?

Upvotes: 0

Views: 77

Answers (1)

David K
David K

Reputation: 124

You could use a function to do this. Note, I don't do any error checking on the range, but isn't difficult to do.

-- subtypes
subtype FIELD is natural range 3 downto 0;

-- functions
function test_func(a: std_logic_vector) return std_logic_vector is
    variable result : std_logic_vector(a'left downto a'right) := a;
begin
    result(FIELD) := (others => '1');
    return result;
end function;

-- constants
constant ALL_ZEROS  : std_logic_vector(7 downto 0) := (others => '0');

-- signals
signal reg          : std_logic_vector(7 downto 0) := test_func(ALL_ZEROS);

Upvotes: 1

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