CODEWITHSUNDEEP
mipscomputer-sciencecpu-architecturemachine-instruction
pizzaguy
pizzaguy

Reputation: 1

Computer Architecture Instructions homework

I do not expect detailed answer since this is just a homework and I do not want to waste everyone's time.

I have a question about something that looks like MIPS code.

We have the 'M' machine that is a memory-memory architecture that has the instruction:

'mmul.d a,b,c'

Which takes the 64-bit floating-point values at b and c and are stored at memory address a.

Then, we have a smaller embedded 'J' machine that translates the 'M' machine's instructions into one or more 'J' Machine instructions:

lw     r1,a      // load 32 bits starting at 'a'
sw     r1,a      // store 32 bits starting at 'a'
pack   f0,r1,r2  // pack two 'r' registers into one 'f' register
unpack f0,r1,r2  // unpack one 'f' register into two 'r' registers
mul.d  f0,f2,f4  // perform floating-point multiply f2 * f4

Now I have to write a J-Machine program that implements 'mmul.d a,b,c'

But I do not understand how the 64 bits machine memory addresses can be loaded into a 32 bits registers. What I thought if we can devide the memory addresses by 2:

lw r1, b
sw r2, b[0]
sw r3, b[1]
lw r1, c
sw r4, c[0]
sw r5, c[1]
pack f2, r2, r3
pack f4, r4, r5
mul.d f0, f2, f4

First I do not know what's the point of loading and storing words, since we can juste store a value in a register with store word.

If you have any documentation and or explanation on how these 32-bit and 64 bit communicate with each other it would be helpful.

Upvotes: 0

Views: 211

Answers (1)

Stefan Haustein
Stefan Haustein

Reputation: 18813

J does not seem to be able to load 64 bit float registers from memory, so you'll need to work around this limitation with intermediate 32 bit integer registers. Probably should look similar to this:

lw r1, b
lw r2, b + 4
pack f1, r1, r2

lw r1, c
lw r2, c + 4
pack f2, r1, r2

mul.d f0, f1, f2

unpack f0, r1, r2
sw r1, a
sw r1, a + 4

Upvotes: 1

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