CODEWITHSUNDEEP
vhdl
P. Lance
P. Lance

Reputation: 189

D-latch with both asynchro and synchro resetting in VHDL

I have to implement a D-latch that follows asynchronnous resetting when aclrn=0 and synchronnous when sclrn=0. The implementation should be able to follow both methods of resetting.

Here's what I came up with in VHDL (I only include the process) based on basic D-latches.

 process(aclrn,clock)
 begin
 if (aclrn='0') then
 q <= '0';
 elsif (rising_edge(clock)) then
     if (sclrn='0') then
     q <= '0';
     else 
     q <= d;
 end if;
end if;
end process;

where

clock, d, aclrn, sclrn : in std_logic; q : out std_logic

Am I correct that the process doesn't need to take in sclrn as an argument, but only aclrn and clock? Are there any other inconsistencies?

Thank you in advance.

Upvotes: 0

Views: 599

Answers (1)

Laleh
Laleh

Reputation: 475

You say D-latch but coded flipflop. Do you really need a D-latch or you are just using latch instead of register carelessly? if you really need a flipflop, you have done it right. You have put aclrn and clock in sensitivity list which is right. You don't need to put sclrn in list because it is synchronous. Xilinx XST tutorial example for Flip-Flop With Positive-Edge Clock and Synchronous Set

architecture archi of registers_3 is
begin
    process (C)
    begin
        if (C'event and C='1') then
            if (S='1') then
                Q <= '1';
            else
                Q <= D;
            end if;
        end if;
    end process;
end archi;

and XST coding example for Flip-Flop With Positive-Edge Clock and Asynchronous Reset

architecture archi of registers_2 is
begin
    process (C, CLR)
    begin
        if (CLR = '1')then
            Q <= '0';
        elsif (C'event and C='1')then
            Q <= D;
        end if;
    end process;
end archi;

By mixing these two you get your answer. I see nothing wrong with your code. best way to know if you've code what you are asked is to simulate it.

If you need latch, notice that latches are sensitive to levels instead of edges. this is an example of LATCH with positive gate and async reset

 architecture archi of latches_2 is
    begin
        process (CLR, D, G)
        begin
            if (CLR='1') then
                Q <= '0';
            elsif (G='1') then
                Q <= D;
            end if;
        end process;
    end archi;

Upvotes: 2

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