CODEWITHSUNDEEP
booleanlogicverilogsystem-verilog
Abraham Lincoln
Abraham Lincoln

Reputation: 57

Harris HDL example 4.13

I read a book called "Digital design and computers architecture" written by Harris and I have a question about example 4.13 (logic gates with delays).

In that example we build a model for the expression Y = !A*!B*!C + A*!B*!C + A*!B*C. And also, we add a few delays to it: 1ns for inverters, three-input AND gates have a delay of 2ns, three-input OR gates have a delay of 4 ns.

Now, the .sv-code below:

*timescale 1ns/1ps
module example(input a,b,c
               output y);
logic ab,bb,cb,n1,n2,n3;
assign #1 {ab,bb,cb} = ~{a,b,c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;

endmodule

So, the question is: what is the logic of such form of programming 3 operands (!A*!B*!C , A*!B*!C , A*!B*C). I don't understand what's happening on the lines from 4 to 8.

Can anyone explain please? Why there are such operands like ab, bb and cb?

Upvotes: 0

Views: 163

Answers (1)

Unn
Unn

Reputation: 5098

ab, bb, and cb are all the logical inverses of a, b, and c (ie, !A, !B, and !C from your logical expression). The "b" or "_B" suffix is often used to indicate the inverse or inverse assertion level.

The assign expression each represent an operation from the original boolean equation:

assign #1 {ab,bb,cb} = ~{a,b,c};

This expression can be thought of as 3 NOT gates with inputs a, b, and c, with outputs ab, bb, and cb respectively. It uses the Verilog bitwise inverse operator ~ as well as the Verilog concatenation operator {} to do the inverse all in one line rather than 3 separate assign expressions.

From there, the assignments of n1, n2, and n3 all correspond to the 3, 3-way and operations in the equation and simply serve as intermediate values in the expression. n1 gets assigned !A * !B * !C, n2 gets A * !B * !C and n3 gets A * !B * C. Notice that each of these has the delay #n for the given gate, with the inverses gets #1; n1, n2 and n3 getting #2 and finally the output y being assigned with the #4 delay as its the final 3-way OR of the ANDed values n1, n2, n3.

Upvotes: 2

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