CODEWITHSUNDEEP
system-verilogvlsiasicsystem-verilog-assertions
Anand
Anand

Reputation: 363

How can I use $display statement within sequence block, to display some info in System Verilog Assertions (SVAs)?

I want sequence blocks to display some information, while they are being executed.

e.g.:

sequence A;
 a;
 $display ("Signal A asserted here");
endsequence

I tried this code, but encountered the following error:

Task $display is invoked where function is expected. Please correct the task call and recompile.

How do I overcome this?

Upvotes: 2

Views: 1328

Answers (2)

Greg
Greg

Reputation: 19112

You can invoked a $display within sequence expression with the syntax (sequence_expr, sequence_match_item) where sequence_match_item can be a operator_assignment, inc_or_dec_expression, or subroutine_call. 

sequence A;
 (a, $display("Signal A asserted here"));
endsequence

Refer to IEEE Std 1800-2012 § 16.11 Calling subroutines on match of a sequence, which has a direct example of $display being invoked within a sequence.

Upvotes: 2

HimanshuD
HimanshuD

Reputation: 3

You can use an "always" block for the $display statements.

Upvotes: 0

Related Questions