CODEWITHSUNDEEP
verilog
Hayder Al-Amily
Hayder Al-Amily

Reputation: 347

How $display works in verilog

At the point where $display appears in this code, there is an error. Why?

module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk)
if (reset)  begin
   data <= 0;
end else if (enable) begin   
   data <= q_in;
end
     $display("data=%d", data);   
endmodule

The error message is:

10: syntax error 10: error: invalid module item

Upvotes: 0

Views: 9187

Answers (1)

DBB
DBB

Reputation: 487

You need to put display within the always block.

module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk) begin
    if (reset)  begin
       data <= 0;
     end else if (enable) begin   
       data <= q_in;
     end

     $display("data=%d", data);
end 

endmodule

You still need to put an initial block to initialize the variables and change them. You also need to create a clock. Things will be a lot clearer if you look at some tutorials for Verilog and understand on how to create a test bench and a design module.

Upvotes: 2

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