CODEWITHSUNDEEP
system-verilogsystem-verilog-assertions
Szt13
Szt13

Reputation: 21

bit width of concatenated arrays in system verilog

I have multiple functions that generate concatenated array of 1 bit variables/defines/enums. Everytime a concatenation happens i want to make sure the final size is 32 bits wide. And flag an error if it is less than or greater than 32 bits. i have tried $bits, $size, but they seem to be wanting a variable and provide the variable width not the width of concatenation. which defeats the purpose.

Any help is appreciated.

Thanks!

here is what i was thinking :- For example. 

logic [31:0] var_out;


function f1(bunch of inputs generated by macros(variable no. of input) a,b,c)
size({a,b,c}); 
var_out = {a,b,c};
endfunction

function f2(bunch of inputs generated by macros(variable no. of input) e,f,g,h,i) 
size({e,f,g,h,i});
var_out = {e,f,g,h,i};
endfunction

function size (in) **// what should be in this function ?**
if(length(in)!=32) - $error("msg"); *// this is what i want to achieve*

Upvotes: 0

Views: 765

Answers (1)

dave_59
dave_59

Reputation: 42623

Nothing in SystemVerilog that takes a number of arguments lets you define it to take a variable number of arguments. (you can have default arguments, but there is no way of knowing from inside the function if the default was used)

Why not 

function f1(bunch of inputs generated by macros(variable no. of input) a,b,c)
  size_check($bits({a,b,c})); 
  var_out = {a,b,c};
endfunction
function void size (int in) **// what should be in this function ?**
if(in !=32) - $error("msg"); *// this is what i want to achieve*
endfunction

Upvotes: 0

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