CODEWITHSUNDEEP
arraysconcatenationverilogsystem-verilog
sara8d
sara8d

Reputation: 413

Concatenation of 2 arrays

I have the following member in transaction:

bit [31:0] data [$];

The interface has the following input:

 logic [31:0] WDATA

In the driver, I want to assign the concatenation of the transaction data to itself. For example if the data contains FFFFFFFF, I have to concatenate FFFFFFFF to FFFFFFFF, and then assign it to the virtual interface

pseudo code: 

vif.DATA <= trx.data[i] (concatenation) trx.tata[i]

How can I do it?

Upvotes: 1

Views: 80

Answers (1)

toolic
toolic

Reputation: 62037

Use the concatenation operator {} (refer to IEEE Std 1800-2012, section 11.4.12 Concatenation operators):

vif.DATA <= {trx.data[i], trx.tata[i]}

Upvotes: 1

Related Questions