CODEWITHSUNDEEP
arraysverilog
bledi
bledi

Reputation: 301

concatenate inputs in verilog

In my module I am taking two input 8-bits.

mymodule(input clk, input [7:0] AS_1,input [7:0] AS_2, output [7:0] AS)

Now I want to create a container that will keep both inputs, I mean I want to join them in a single one. I want to do something like that:

reg [15:0] JOIN = AS_1 and AS_2 ---> all their bits should be arranged in a single container

But I don't know whether it should be a reg type or wire or something else, because I'll need to make other operations with that JOIN

Any help, advise or suggestion would be highly appreciated!!!

Upvotes: 2

Views: 20356

Answers (1)

Tim
Tim

Reputation: 35923

It can be reg or wire, you assign them slightly different but the result is the same:

wire [15:0] join;
assign join = {AS_1, AS_2}; //concatenation operator

or:

reg [15:0] join;
always @* begin
    join = {AS_1, AS_2};
end

In either case you can use the value of join exactly the same.

Upvotes: 6

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