CODEWITHSUNDEEP
arraysverilog
Awais Hussain
Awais Hussain

Reputation: 442

How to flatten array in Verilog

As Verilog does not allow to pass the array as input to module, so how can we flatten any array in Verilog. Suppose I have this array:

parameter [31:0] A [0:31];
wire [31:0] B

I want to pass this into any module like:

module1 M1 (.input(A), .output (B));

How can I achieve this?

Upvotes: 1

Views: 9778

Answers (1)

grorel
grorel

Reputation: 1466

This verilog restriction is just a pain in... and etc... but we have to deal with it.

You can map the 2D array onto a 1D array like this :

wire [32*32-1:0]One_D_array;
integer i;
for (i=0; i<32; i=i+1) assign One_D_array[32*i+31:32*i] = A[i];

Then in your module, you can recreate the 2D array with the inverted for loop :

wire [31:0]local_2D_array[0:31];
integer i;
for (i=0;i<32;i=i+1) assign local_2D_array[i] = input[32*i+31:32*i];

The synthesis tool will handle it as wire remapping, so no LUT/FLIP_FLOP will be used. This is the easiest workaround I found for this limitation.

Upvotes: 4

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