problem with flattening an array in verilog

Question

I tried to flatten an array with numbers into a variable in order to pass it as an input to a module in verilog. But, I get the error:

Port 1 (DATA_IN) of process_data expects 64 bits, got 4096. Pruning 4032 high bits of the expression.

I know that my module process_data in not ready yet and hence it does not work properly, but my problem for now is that the input is a lot more bits than it should. Do you know how could I fix it?

module process_data(input wire [63:0] DATA_IN , input wire  [6:0]AdrR , input wire  [6:0]AdrW,  input R_W , input Cen,                                     input clk, input reset,  output reg [63:0]Reg_Data_Out);

  integer i;
  reg [63:0]Memory[63:0];       //64 * 64 bit array   
  initial 
   begin
    i=0;
     //++for 
     repeat (64)
      begin
        Memory[i]=64'd1;            //64 = number of the thesis that the vector has
        i=i+1;
      end
  end

  always @(negedge(clk))
    //initial AdrR ,AdrW = 0;  // 7'b0000_000;
    begin
    if(Cen == 1'b1) begin  // cen = chip enabled 
    case (R_W)   
      1'b1:
        //++check if not empty 
        Reg_Data_Out = Memory[AdrR];      // (read)  out put memory context           

      1'b0:
        //++check if not full 
        Memory[AdrW] = DATA_IN;              // write input to memory 
      default:
        Reg_Data_Out = 64'bxxxxxxxx;  
    endcase  
  end
  end

endmodule 

module TOP();

  reg [63:0] inputdata1 [0:127];          //array 
  reg [64*64-1:0] flattened_inputdata1;
 reg [6:0] AddressR,AddressW;

  reg cen,clk, R_W, reset;  
  wire [63:0] Data_Out;

  //pass the numbers
  integer count;

  initial
  begin
    count = 0;
    while (count < 128) // Execute loop till count is 127. exit at count 128
      begin
      // every timh that the integer variable count takes must be also passed into reg inputdata1 
        inputdata1[count] = count;
      count = count + 1;
   end
  end

   //flattening 
  initial
  begin
    count = 0;
    while (count < 128)  // Execute loop till count is 127. exit at count 128
      begin
        flattened_inputdata1[64*count +: 64] = inputdata1[count];
        //flattened_inputdata1[(64*count) +63) : (64*count)]  =  inputdata1[count];  //declare a number is dekadikos 
        count = count + 1;

    end
  end

  //call module for data I/O 
  process_data process_data( flattened_inputdata1, AddressR, AddressW, R_W , cen, clk, reset, Data_Out);    //reset does not do anything yet

  always #10 clk=~clk;

  initial
  begin
    $display("flattenedinputdata1=%d", flattened_inputdata1);
    cen=1'b1;   //chip enabled 

     #50
    R_W=1'b1;   //read
    AddressR=7'b0000_000;

    #50
    //R_W=1'b1;    //read
    //AddressR=7'b0000_001;

    $finish;   //#50 $finish;
   end

endmodule

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Answer 1

You can see from the declarations that the sizes are different:

input wire [63:0] DATA_IN

and the thing you're passing in to it:

reg [64*64-1:0] flattened_inputdata1;

DATA_IN is 64 bits and flattened_inputdata1 is 4096 bits. So you'll need to change one of them so that the two sizes match.