CODEWITHSUNDEEP
arraysverilog
mike_b
mike_b

Reputation: 2367

array input never used

I'm trying to make a register array, and want to eliminate a warning. I've created a minimal example design below. Why is part of addr unused?

When I synthesize I get the warning:
WARNING:Xst:647 - Input <addr<3:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

module test(addr,in,out,wr,clk);
input [3:0] addr;
input [7:0] in;
output reg [7:0] out;
input wr;
input clk;
reg [7:0] ra [0:3];

always @(posedge clk)
begin
    if (wr)
        ra[addr] = in;
    else
        out <= ra[addr];
end
endmodule

I'm trying to make a register that is 8 bits wide with 16 addresses (0-15).

Upvotes: 1

Views: 226

Answers (1)

sharvil111
sharvil111

Reputation: 4381

Following part of the given warning is important.

Input "addr3:2" is never used.

Here, addr is four bits and ra is declared as reg [7:0] ra [0:3];. Assuming ra is termed as register-array (memory). This declares a memory of 4-byte.

For addressing 4 bytes, only two bits are sufficient. So, the addresses goes as 00,01,10,11 only. The upper bits of addr are never used i.e. bits 3:2 are unused in any case. Hence the warning is issued.

For 16-bytes of memory, you need to declare ra as reg [7:0] ra [0:15];, by this all the bits of addr shall be used up and warning should be removed.

Now for the second part of warning.

This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Even though the bits are unused, they will be preserved by the synthesis tool and left unconnected. In case these lines are available in top-instantiating block. This is quite a reasonable thing to understand.

Upvotes: 6

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