CODEWITHSUNDEEP
cachingoperating-systemhardwarecpu-architecture
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Reputation: 362

In what case would a uniprocessor system invalidate it's cache?

Is there any scenario where a single processor (or single core) system would invalidate it's cache line?

Since there is no need for coherence, invalidation from other cores is out of the question.

Is there hardware support for timer invalidation of a cache line?

When a program exits, (how) are the cache lines related to it invalidated? I'm assuming the OS would not know cache implementation so it won't invalidate.

Upvotes: 0

Views: 309

Answers (2)

Leeor
Leeor

Reputation: 19736

In addition the Isuru's answer - Sometimes the user wants to invalidate all copies of some line, usually for fault tolerance (sometimes this can involve writing to some non-volatile memory, but caches may still be lost so you need to make sure no fresh data remains there). I can also think of some security purposes (cache sniffing by other rocesses).

However, I think the most common cause are some powerdowns/sleep states of the CPU that may put some components to sleep (including some caches), for example when waiting for some external event.

Upvotes: 2

Isuru H
Isuru H

Reputation: 1221

I can think of few situations.

  1. If your cache is "write bypass", writes only invalidate the cache line and update the main memory.

  2. Memory mapped I/O, so a cached memory location can be modified by an I/O device. This is similar to a simplified cache coherent system.

  3. Also when paged are swapped, virtual to physical translation in TLB is not valid, so the entry is marked invalid. Accordingly cache entry become invalid as physical address is not correspond to the cached entry anymore.

Existing a program is similar to swapping a page, so I guess the 3 point answers the question.

AFAIK, there is no timed invalidations, although you can issue an invalidate instruction later in the instruction stream.

Upvotes: 2

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