CODEWITHSUNDEEP
xilinx
Cindy
Cindy

Reputation: 183

Xilinx error: Port connections cannot be mixed ordered and named

FA FA9(.in0(CSA10[0]), .in1(CSA11[0]), .carry_in(CSA12[0]), .sum(CSA20[0]), carry_out(CSA20[1]));

For the above line of code, I got error "Port connections cannot be mixed ordered and named". All the CSAs are declared as wire [1:0] CSA11, CSA12, etc. The tool I am using is Xilinx 14.7.

I think the port connection I am using in the above statement is only named connection.

Thanks in advance!

Upvotes: 2

Views: 10985

Answers (1)

cecomp64
cecomp64

Reputation: 687

Looks like you missed the "." before "carry_out". Try this:

FA FA9(.in0(CSA10[0]), .in1(CSA11[0]), .carry_in(CSA12[0]), .sum(CSA20[0]), .carry_out(CSA20[1]));

Upvotes: 2

Related Questions