CODEWITHSUNDEEP
vhdl
Aaron
Aaron

Reputation: 2475

VHDL record is not fully constrained

I have an interface record that gets created via a function, but when I try to compile I get an error about the interface being unconstrained.

The record:

type t_my_if is record
    wdata : std_logic_vector;
    wen   : std_logic;
end record;

Function declaration:

function init_my_if_signals(data_width : natural) return t_my_if;

Function body:

function init_my_if_signals(data_width : natural) return t_my_if is
    variable init_if : t_my_if(wdata(data_width - 1 downto 0));
begin
    init_if.wdata := (others => '0');
    init_if.wen   := '0';
    return init_if;
end function;

Note that although one of the record parameters is a std_logic_vector, it's size gets defined when created through the initialization function. So I am not sure why I get the following error:

(vcom-1361) Subtype of "my_if" is not fully constrained.

The interface is on an inout port of the entity, so it looks something like:

my_if   : inout t_my_if := init_my_if_signals(8)

EDIT:

The following code works, but I want to be able to dynamically define a data width, so this solution is not optimal for me.

New record:

type t_my_if is record
    wdata : std_logic_vector(7 downto 0;
    wen   : std_logic;
end record;

New function:

function init_my_if_signals(data_width : natural) return t_my_if is
    variable init_if : t_my_if;
begin
--same as above

Can I not define this when the record is instantiatied?

Upvotes: 2

Views: 2250

Answers (2)

JHBonarius
JHBonarius

Reputation: 11271

So according to Doulos VHDL 2008 small changes, this is allowed in VHDL-2008. Their example:

type myRecordT is
record
  a : std_logic_vector;
  b : std_logic_vector;
end record;

variable R : myRecordT( a(7 downto 0), b(15 downto 0) );

Are your compiling in VHDL-2008 mode?

edit:

my_if   : inout t_my_if := init_my_if_signals(8)

there's you problem: the t_my_if part is unconstrained. Try:

my_if   : inout t_my_if(wdata(7 downto 0)) := init_my_if_signals(8)

By the way: inout ports are bad, m'kay? (unless you know what you're doing)

Upvotes: 1

fpga_magik
fpga_magik

Reputation: 89

How about declaring all constants and widths in a package and defining the required type with the correct widths before using them in the inteface.

package my_if_pkg is
    constant c_data_width : natural := 8;

    type t_my_if is record
        wdata : std_logic_Vector(c_data_width-1 downto 0);
        wen   : std_logic;
    end record;

    constant z_my_if : t_my_if := ( wdata => (others => '0'),
                                    wen   => '0' );
end package;
...

Then use the package within the interface:

use my_if_pkg.all;
...

my_if : inout t_my_if := z_my_if;

Upvotes: 0

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