CODEWITHSUNDEEP
system-verilog
PieterNuyts
PieterNuyts

Reputation: 579

How is SystemVerilog 0 different from '0?

When executing the following piece of SystemVerilog code (compiled and run with Questa)

bit [7:0] test = 255;
$display("%b %b %b", test,        test == 255,      test == '1);
$display("%b %b %b", ~test,       ~test == 0,       ~test == '0);
$display("%b %b %b", 8'b00000000, 8'b00000000 == 0, 8'b00000000 == '0);

the output is

11111111 1 1
00000000 0 1
00000000 1 1

My question is about the 2nd number on the 2nd output line: How is binary 00000000 different from 0? And why is it only different if it is the result of ~test, and not when it is a literal? Is this a Questa bug or a property of the language?

Upvotes: 5

Views: 11363

Answers (1)

dave_59
dave_59

Reputation: 42698

The difference is that 0, without any width prefix defaults to 32-bit value. In an equality, the operands get sized to the maximum width between the expressions on the LHS and RHS expressions before evaluating those expressions. Try ~test == 9'h0 and ~test == 9'h100 and see what you get.

The size of '0 is based on its context. So ~test =='0 become ~test == 8'b0 in that context.

Upvotes: 9

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