CODEWITHSUNDEEP
system-verilog
penguin_king
penguin_king

Reputation: 37

|-> meaning in systemverilog

What does |-> mean in systemverilog?

For example:

$fell(clkreq_hold) |-> ##1 $past(clkreq)

What's the difference between |-> and -> ?

Upvotes: 1

Views: 989

Answers (1)

dave_59
dave_59

Reputation: 42698

-> is a logical implication operator (See 11.4.7 Logical operators) A->B is equivalent to the Boolean expression !A || B.

|-> is a property operator for overlapping implication. (See section 16.12.7 in the SystemVerilog IEEE 1800-2017 LRM) sA |->pB in the clock cycle when sequence sA succeeds, begin an attempt to see if property pB succeeds. When sA and pB are both simple Boolean expressions, they appear as if they have the same functionality. Except, when sA is false, the implication is considered a vacuous success. (excluded from the successful passing's count)

Upvotes: 4

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