Lattice Diamond: Found inferred clock

Question

I am working on a project for a class and I ran into to problem. My task is to draw a registry scheme. I did so but I get warning and my test results are wrong. The warning that I get is :

2019993 WARNING - MT420 |Found inferred clock SCHEMA1|C with period 1000.00ns. Please declare a user-defined clock on object "p:C"
2019991 WARNING - MT529 :"c:\"|Found inferred clock SCHEMA1|C which controls 8 sequential elements including I25. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
Signals gnd and vcc are undriven.

And my vhd code is this.

library IEEE;
use IEEE.std_logic_1164.all;
library xp2;
use xp2.components.all;

entity SCHEMA1 is
      Port (       C : In    std_logic;
                 rst : In    std_logic;
                  DR : In    std_logic;
                  Q7 : Out   std_logic;
                  D7 : In    std_logic;
                  A0 : In    std_logic;
                  A1 : In    std_logic;
                  Q6 : Out   std_logic;
                  D6 : In    std_logic;
                  Q5 : Out   std_logic;
                  D5 : In    std_logic;
                  Q4 : Out   std_logic;
                  D4 : In    std_logic;
                  Q3 : Out   std_logic;
                  D3 : In    std_logic;
                  Q2 : Out   std_logic;
                  D2 : In    std_logic;
                  Q1 : Out   std_logic;
                  D1 : In    std_logic;
                  DL : In    std_logic;
                  Q0 : Out   std_logic;
                  D0 : In    std_logic );

end SCHEMA1;

architecture SCHEMATIC of SCHEMA1 is

   SIGNAL gnd : std_logic := '0';
   SIGNAL vcc : std_logic := '1';

   signal     N_17 : std_logic;
   signal     N_16 : std_logic;
   signal Q0_DUMMY : std_logic;
   signal Q1_DUMMY : std_logic;
   signal Q2_DUMMY : std_logic;
   signal Q3_DUMMY : std_logic;
   signal Q4_DUMMY : std_logic;
   signal Q5_DUMMY : std_logic;
   signal Q6_DUMMY : std_logic;
   signal Q7_DUMMY : std_logic;
   signal      N_1 : std_logic;
   signal      N_2 : std_logic;
   signal      N_3 : std_logic;
   signal      N_4 : std_logic;
   signal      N_5 : std_logic;
   signal      N_6 : std_logic;
   signal      N_7 : std_logic;
   signal      N_8 : std_logic;
   signal      N_9 : std_logic;
   signal     N_10 : std_logic;
   signal     N_11 : std_logic;
   signal     N_12 : std_logic;
   signal     N_13 : std_logic;
   signal     N_15 : std_logic;

   component fd1s3ax
      Port (      CK : In    std_logic;
                   D : In    std_logic;
                   Q : Out   std_logic );
   end component;

   component mux41
      Port (      D0 : In    std_logic;
                  D1 : In    std_logic;
                  D2 : In    std_logic;
                  D3 : In    std_logic;
                 SD1 : In    std_logic;
                 SD2 : In    std_logic;
                   Z : Out   std_logic );
   end component;

   component and2
      Port (       A : In    std_logic;
                   B : In    std_logic;
                   Z : Out   std_logic );
   end component;

begin

   Q7 <= Q7_DUMMY;
   Q6 <= Q6_DUMMY;
   Q5 <= Q5_DUMMY;
   Q4 <= Q4_DUMMY;
   Q3 <= Q3_DUMMY;
   Q2 <= Q2_DUMMY;
   Q1 <= Q1_DUMMY;
   Q0 <= Q0_DUMMY;

   I25 : fd1s3ax
      Port Map ( CK=>C, D=>N_17, Q=>Q7_DUMMY );
   I7 : fd1s3ax
      Port Map ( CK=>C, D=>N_12, Q=>Q6_DUMMY );
   I6 : fd1s3ax
      Port Map ( CK=>C, D=>N_10, Q=>Q5_DUMMY );
   I5 : fd1s3ax
      Port Map ( CK=>C, D=>N_16, Q=>Q4_DUMMY );
   I4 : fd1s3ax
      Port Map ( CK=>C, D=>N_7, Q=>Q3_DUMMY );
   I3 : fd1s3ax
      Port Map ( CK=>C, D=>N_5, Q=>Q2_DUMMY );
   I2 : fd1s3ax
      Port Map ( CK=>C, D=>N_3, Q=>Q1_DUMMY );
   I1 : fd1s3ax
      Port Map ( CK=>C, D=>N_1, Q=>Q0_DUMMY );
   I24 : mux41
      Port Map ( D0=>Q7_DUMMY, D1=>DR, D2=>Q6_DUMMY, D3=>D7, SD1=>A0,
                 SD2=>A1, Z=>N_15 );
   I23 : mux41
      Port Map ( D0=>Q6_DUMMY, D1=>Q7_DUMMY, D2=>Q5_DUMMY, D3=>D6,
                 SD1=>A0, SD2=>A1, Z=>N_13 );
   I22 : mux41
      Port Map ( D0=>Q5_DUMMY, D1=>Q6_DUMMY, D2=>Q4_DUMMY, D3=>D5,
                 SD1=>A0, SD2=>A1, Z=>N_11 );
   I21 : mux41
      Port Map ( D0=>Q4_DUMMY, D1=>Q5_DUMMY, D2=>Q3_DUMMY, D3=>D4,
                 SD1=>A0, SD2=>A1, Z=>N_9 );
   I20 : mux41
      Port Map ( D0=>Q3_DUMMY, D1=>Q4_DUMMY, D2=>Q2_DUMMY, D3=>D3,
                 SD1=>A0, SD2=>A1, Z=>N_8 );
   I19 : mux41
      Port Map ( D0=>Q2_DUMMY, D1=>Q3_DUMMY, D2=>Q1_DUMMY, D3=>D2,
                 SD1=>A0, SD2=>A1, Z=>N_6 );
   I18 : mux41
      Port Map ( D0=>Q1_DUMMY, D1=>Q2_DUMMY, D2=>Q0_DUMMY, D3=>D1,
                 SD1=>A0, SD2=>A1, Z=>N_4 );
   I17 : mux41
      Port Map ( D0=>Q0_DUMMY, D1=>Q1_DUMMY, D2=>DL, D3=>D0, SD1=>A0,
                 SD2=>A1, Z=>N_2 );
   I16 : and2
      Port Map ( A=>N_15, B=>rst, Z=>N_17 );
   I15 : and2
      Port Map ( A=>N_13, B=>rst, Z=>N_12 );
   I14 : and2
      Port Map ( A=>N_11, B=>rst, Z=>N_10 );
   I13 : and2
      Port Map ( A=>N_9, B=>rst, Z=>N_16 );
   I12 : and2
      Port Map ( A=>N_6, B=>rst, Z=>N_5 );
   I11 : and2
      Port Map ( A=>N_4, B=>rst, Z=>N_3 );
   I10 : and2
      Port Map ( A=>N_2, B=>rst, Z=>N_1 );
   I9 : and2
      Port Map ( A=>N_8, B=>rst, Z=>N_7 );

end SCHEMATIC;

I did not change any of this code. I just draw a scheme and got these odd errors for me... Any solution that I found so far is suggesting to write something on sdc file or something, but our task doesnt require this, it should work without changing code. Also i didnt even use gnd and vcc signal they were created for me and they been in any other task ive done and never had this warning before.

Lattice Diamond: Found inferred clock

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