CODEWITHSUNDEEP
system-veriloguvm
Pete
Pete

Reputation: 49

Overriding constraints

I am having some trouble overriding constraints in my testbench. In my sequence I am doing the following:

    `uvm_do_with(req, {trans_kind == WRITE ;
                       address == 40'hc0_0000_0000;
                       mask_mismatch_error == 1;
                       bus_error_type == SCB_BUS_ERR_NONE;
                       }) //this line sends the transaction

And in my sequence item:

    constraint c_mask_mismatch_error_disable_map8 { (cfg_h.is_map8 == 1) -> (mask_mismatch_error == 0); }

The log file is giving this warning:

ncsim: *W,SVRNDF (source location/line): The randomize method call failed. The unique id of the failed randomize call is 86.

Observed simulation time : 79492842 PS + 14

ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints: }) //this line sends the transaction ( (mask_mismatch_error == 0); } (source location/line)

ncsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints:

state variables: cfg_h.is_map8 (1) [source location/line]

rand variables: mask_mismatch_error [source location/line]

I don't understand why this type of override is not possible. What can I do to be able to override the constraint from the sequence?

Upvotes: 1

Views: 5070

Answers (1)

dave_59
dave_59

Reputation: 42698

The with clause of a call to randomize is only used to add constraints; it cannot override them. The proper OOP way to override a constraint is to extend your transaction class and declare a constraint with the same name in the extended class.

Your other option is to turn the constraint off using

req.c_mask_mismatch_error_disable_map8.constraint_mode(0);

If you do that, you can no longer use the `umm_do_with macro, which many people recommend against using anyways.

Upvotes: 1

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