CODEWITHSUNDEEP
cachingmemory-managementmips
nawdeh naw
nawdeh naw

Reputation: 51

Direct mapped cache in MIPS

I have a direct mapped instruction cache on a 32-bit MIPS processor. The capacity is 2048 bytes and the block size is 16 bytes. Assume that 10 instructions are executed in each iteration of a loop. Before the loop starts, we can assume that the cache is empty (all valid bits are set to zero). The first instruction in the loop starts at address 0x00400200.

What is then the cache hit rate when executing the loop, if the loop iterates 10 times?

Upvotes: 0

Views: 1442

Answers (1)

markgz
markgz

Reputation: 6266

The block size is 16 bytes, so 10 instructions fit into three blocks.

On the first execution of the loop instruction 1 (I1) will miss. I2,I3,I4 will hit, since the first block was loaded when I1 was read from memory. Then I5 will miss and I6,I7,I8 will hit. Then I9 will miss and I10 will hit.

I1, I5 and I9 miss on the first iteration. There are no misses on subsequent loop iterations. Therefore the hit rate is 100 - 3 = 97%.

Upvotes: 1

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