CODEWITHSUNDEEP
cachingmipscpu-architecture
user977154
user977154

Reputation: 1095

Direct Map Cache and cache misses

I am working on my homework, but I am not sure how to calculate the total cache misses. I have been trying to understand it but it just is not making sense to me. I am given some Mips code and I need to calculate the number of cache misses. Here is the problem:

Direct-map cache. We are given a direct-map cache with 1024 blocks. Each block is a MIPS word (32 bits). The cache uses write-back whenever a write miss happens. The main memory consists of 2^30 words. Initially, the cache is empty.
Determine the total number of cache misses for the following instruction sequences. 

lw $s0, 4($sp) 
lw $s0, 8($sp) 
sw $s0, 8($sp) 
sw $s1, 4($sp) 
lw $s0, 4($sp)

I am not looking for the answer. I want to learn how to do this because I have many more problems like this on the homework assignment. I would like a walkthrough on this. In the meantime I will be researching this topic trying to figure out the answer.

Upvotes: 2

Views: 1816

Answers (1)

ArtemB
ArtemB

Reputation: 3622

Without knowing alignment of $SP it's impossible to tell how many cache misses you will have. If SP is aligned on 32-byte boundary, then there will be only one cache line miss on the very first access. If SP contains address 0x18, then you will have two cache line misses because 4($sp) and 8($sp) will access different cache lines.

Upvotes: 2

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