Reputation: 163
It is possible to make a partial assignment to a vector IO as follows:
import chisel3._
class example_1 extends Module {
val io = IO(new Bundle {
val in1 = Input(Vec(4, Bool())
val out1 = Output(Vec(4, Bool())
})
for (I <- 0 to 3){
io.out1(I) := io.in1(I)
}
}
Is it possible to make a partial assignment to a multi-bit slice of a vector. The following code doesn't work
import chisel3._
class example_1 extends Module {
val io = IO(new Bundle {
val in1 = Input(Vec(4, Bool())
val out1 = Output(Vec(4, Bool())
})
for (I <- 0 to 1){
io.out1((I*2)+2-1, I*2) := io.in1((I*2)+2-1, I*2)
}
}
One would assume that this should be possible using slice, however, whilst slice works for referencing a slice of the io.in1 vector
val in1_sl = io.in1.slice(0, 2)
It is not possible to use slice on the LHS of the assignment to create a slice of io.out1:
io.out1.slice(0, 2) := io.in1.slice(0, 2)
The example that I've used here is just for demonstration purposes.
Upvotes: 2
Views: 1796
Reputation: 4051
I don't think there is a way to do this currently in chisel. Using slice on the LHS means that the collection returned by splice is not something that supports a connect method. That being said, the following seems to work, though I haven't considered into all the implications of it.
class Slicer extends Module {
implicit class SeqHelper(val seq: Seq[Bits]) {
/**
* Promotes a Seq of Bits to a class that supports the connect operator
*/
def := (other: Seq[Bits]): Unit = {
seq.zip(other).foreach { case (a, b) => a := b}
}
}
val io = IO(new Bundle {
val in1 = Input(Vec(4, Bool()))
val out1 = Output(Vec(4, Bool()))
})
io.out1.slice(0, 2) := io.in1.slice(0, 2)
}
You could put the SlicerHelper in a package object making it generally accessible. Less exotic idioms to consider might be.
io.out1.slice(0, 2).zip(io.in1.slice(0, 2)).foreach { case (a, b) => a:= b }
or
io.out1.zip(io.in1).slice(0, 2).foreach { case (a, b) => a:= b }
Upvotes: 2