CODEWITHSUNDEEP
scalachisel
Lin Frank
Lin Frank

Reputation: 113

How to use "hierarchical path" of chisel/scala?

In verilog there is such a way to access other module's stuff, as I know it was called "hierarchical path", here is a verilog RTL

module A;
  reg a;
endmodule
module tb;
  A u_A();
  wire b;
  assign b = u_A.a; // hierarchical path
endmodule

Could you enlight me how to access Reg/Wire of other Modules in Chisel/Scala?

Upvotes: 0

Views: 729

Answers (1)

Chick Markley
Chick Markley

Reputation: 4051

AFAIK, this is not possible in chisel3. If you try you will get an error

An exception or error caused a run to abort: Connection between sink (chisel3.core.UInt@b) and source (chisel3.core.UInt@1b) failed @: Source is unreadable from current module. 
chisel3.internal.ChiselException: Connection between sink (chisel3.core.UInt@b) and source (chisel3.core.UInt@1b) failed @: Source is unreadable from current module

If you want to expose it to outside modules you should do that through the io mechanism. That being said it is possible to create the syntactic appearance of direct access to the module by using the experimental feature MultiIOModule

import chisel3._
import chisel3.experimental._

class A extends MultiIOModule {
  val reg = Reg(UInt(16.W))
  val r = IO(Output(reg))
  r := reg
}

class B extends MultiIOModule {
  val u_A = Module(new A)
  val b = Wire(UInt(16.W))
  b := u_A.r
}

Upvotes: 1

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