CODEWITHSUNDEEP
verilog
Luca
Luca

Reputation: 23

Vector assignment in Verilog

It is my first attempt to use verilog. I have defined an 8-bit bidirectional port, a data register and a data direction register in the following way:

inout [7:0] pa;  //  8-bit bidirectional parallel port
reg [7:0] data_reg;
reg [7:0] data_dir_reg; // 0 --> input; 1 --> output

assign pa [7] = (data_dir_reg [7]) ? data_reg [7] : 1'bZ;
assign pa [6] = (data_dir_reg [6]) ? data_reg [6] : 1'bZ;
assign pa [5] = (data_dir_reg [5]) ? data_reg [5] : 1'bZ;
assign pa [4] = (data_dir_reg [4]) ? data_reg [4] : 1'bZ;
assign pa [3] = (data_dir_reg [3]) ? data_reg [3] : 1'bZ;
assign pa [2] = (data_dir_reg [2]) ? data_reg [2] : 1'bZ;
assign pa [1] = (data_dir_reg [1]) ? data_reg [1] : 1'bZ;
assign pa [0] = (data_dir_reg [0]) ? data_reg [0] : 1'bZ;

It works perfectly, however, I'm sure, there must be an easier way to accomplish the same result.

I have tried with a for cycle:

integer i;

for (i = 0; i < 8; i = i + 1)
  begin
    assign pa [i] = (data_dir_reg [i]) ? data_reg [i] : 1'bZ;
  end

as well as assigning the whole vector at once:

assign pa [7:0] = (data_dir_reg [7:0]) ? data_reg [7:0] : {8{1'bZ}}[7:0];

without any result. Thanks for any help.

Luca

Upvotes: 2

Views: 8156

Answers (1)

dave_59
dave_59

Reputation: 42623

You want a generate-for loop. 

genvar i;
for (i = 0; i < 8; i = i + 1)
  begin
    assign pa [i] = (data_dir_reg [i]) ? data_reg [i] : 1'bZ;
  end

This gets unrolled into what you originally wrote.

Upvotes: 3

Related Questions