CODEWITHSUNDEEP
shellgccmakefile
Sajjad
Sajjad

Reputation: 121

Makefile to auto compile, assemble and link many files in a directory

Sorry for repetition, but I could not find the solution. Following is the sequence of the commands I want Makefile to accomplish.

gcc-elf-gcc -S -combine loadStoreByte.c string.c lib_uart.c bubble_uart.c -o bubble_uart.s 

gcc-elf-as -o startup.o startup.s;
gcc-elf-as -o handler.o handler.s;
gcc-elf-as -o bubble_uart.o bubble_uart.s;

gcc-elf-ld -o bubble_uart -T browtb.x bubble_uart.o startup.o handler.o;

That is, I want to compile all C files into a single S file and then assemeble all s files into corresponding object files and the link all object files into one executable.

I tried the following makefile. The individual targets work fine, but could not run all the target at the same time using "make all". Please guide how to fix it.

CC = brownie32-elf-gcc
AS = brownie32-elf-as
LK = brownie32-elf-ld
SFILE = $(wildcard *.s)
OFILE = $(patsubst %.s,%,$(SFILE))
CFILE = $(wildcard *.c)
OBJ = $(wildcard *.o)

APP = bubble_uart

all: compile assemble link

link: $(OBJ)
        $(LK) -o $(APP) -T browtb.x $^

assemble: $(OFILE)

%: %.s compile
        $(AS) -o [email protected] $<

compile: $(CFILE)
        $(CC) -S -combine $^ -o $(APP).s

clean: 
        rm -f $(OBJ) $(APP) $(APP).s *.o

Thanks

Upvotes: 0

Views: 1348

Answers (2)

Beta
Beta

Reputation: 99084

It is usually best if the target of a rule is the name of the file the rule produces.

So the compile rule:

compile: $(CFILE)
    $(CC) -S -combine $^ -o $(APP).s

should be this:

$(APP).s: $(CFILE)
    $(CC) -S -combine $^ -o $@

Likewise the object rule:

%: %.s compile
    $(AS) -o [email protected] $<

should be this:

%.o: %.s
    $(AS) -o $@ $<

(There's no reason for it to depend on compile or $(APP).s, since bubble_uart.s is irrelevant to most object files.)

Then the list of object files should include bubble_uart.o:

SFILES = $(sort $(wildcard *.s) $(APP).s)
OFILES = $(patsubst %.s,%.o,$(SFILES))

(The sort is to remove duplicates.) Note that this is the list of object files needed for construction of the executable, not the list of object files that happen to exist at the beginning of the build process.

Finally, the executable:

$(APP): $(OFILES)
    $(LK) -o $@ -T browtb.x $^

Upvotes: 0

Mark Galeck
Mark Galeck

Reputation: 6385

Your makefile is not written with "best practices" and because of that it was easy for you to make mistakes. I will re-write your makefile here, with best practices, which solves all your problems. Please study it with the aid of the GNU Make manual.

The biggest single problem is that you have "procedures/actions", such as "assemble" as make targets. This makes the makefile into a kind of "procedural" program. GNU Make is not designed to be a procedural language, instead, it is a declarative language. The "targets" should not be actions, but actual files, or "phony" files, which should be collections of actual files.

The use of wildcard in makefiles is a bad idea - it is best to list your files explicitly, as I have shown.

Please consult my answer makefile enforce library dependency ordering for a discussion of good practices, including phony and real targets. 

MAKEFILE := $(lastword $(MAKEFILE_LIST))

CFILES := \
    loadStoreByte.c \
    string.c \
    lib_uart.c \
    bubble_uart.c

SFILE_OUTPUT := bubble_uart.s

SFILES := $(SFILE_OUTPUT) \
    startup.s \
    handler.s

OFILES := $(SFILES:s=o)

APP := bubble_uart

.PHONY: all
all: $(APP)

$(APP): browtb.x $(OFILES) $(MAKEFILE)
    gcc-elf-ld -o $@ -T $< $(OFILES)

$(OFILES): %o : %s $(MAKEFILE)
    gcc-elf-as -o $@ $<

$(SFILE_OUTPUT): $(CFILES) $(MAKEFILE)
    gcc-elf-gcc -S -combine $(CFILES) -o $@

Upvotes: 2

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