CODEWITHSUNDEEP
verilog
kevin1494
kevin1494

Reputation: 158

simulation behaviour of enable

I have just started using VCS for compiling and simulating my TB written in verilog.

I am stumped by how it treats the 0->1 or 1->0 transitions. I believe that for evaluation purposes a 0->1 transition is infact seen as a 0 and a 1->0 is seen as a 1. I would expect this behavior in my sims for my design to behave correctly.

But for the life of me I cant figure out why its treating the generated input stimulus' 0->1 transition as 1 and 1->0 as 0

Below is the portion of code relevant for this. Its a simple flop with an enable signal - "en" which is the input stimulus that gets triggered randomly from an event controlled by the same clock, clk. clk is used everywhere in TB and design

always @(posedge clk or negedge reset_) begin
  if (!reset_) begin
    q <= {5{1'b0}};
  end else begin
    if (!en) begin
      q <= d;
    end 
  end
end

Now what happens is that when the event gets triggered, i.e a 0->1 transition happens on en, then I want the flop to see it still as a 0 and flop d. And on the falling edge of en which coincides with another posedge of clk I need to ensure flopping doesnt happen (it should be seen as a 1).

The simulations are doing opposite of what I am expecting unless i slightly delay the en triggering which I dont think is the ideal solution.

Is it wrong to expect such a behavior? If no, then how can I go about fixing this? Any insights would be greatly appreciated.

Please let me know if you need more details.TIA

Upvotes: 3

Views: 764

Answers (1)

Mac
Mac

Reputation: 357

Raising Greg's comment to an answer so this question can be marked as answered:

There will not be a race condition if you assign clk with a blocking statement (=) and assign en with a non-blocking statement (<=). This is is the proper coding style. Then the only thing you need to remember is the sampled value of en and d is the left side if the clock edge. – Greg Oct 26 '17 at 14:44

Upvotes: 0

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