CODEWITHSUNDEEP
syntaxsystem-verilog
user121330
user121330

Reputation: 229

"Expecting a description" error in systemverilog when instantiating a class

I think my Quartus is broken, but I'm hoping for a syntax error (the semi-colons look right). I stole this exact code from here, and since it doesn't work I'm hoping somebody knows what to check in Quartus to get this to compile.

Code:

class C;
  int x;
  task set (int i);
    x = i;
  endtask
  function int get;
    return x;
  endfunction
endclass

Error:

Picture of Error

Error text:

Error (10170): Verilog HDL syntax error at enable_logic_tb.sv(42) near text: "class";  expecting a description. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Upvotes: 1

Views: 1161

Answers (1)

dave_59
dave_59

Reputation: 42698

Quartus does not synthesize classes. The class construct is only for simulation.

Upvotes: 2

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