CODEWITHSUNDEEP
verilog
DesertEagle_PWN
DesertEagle_PWN

Reputation: 81

"Identifier not declared" in Verilog. Anyone know why I'm getting this?

Been working for a while on figuring this problem out, but brief searches produced nothing and Verilog syntax guides don't seem to provide any useful information. I am compiling these two Verilog files together along with another that consists solely of the pre-made gates (ANDs, ORs, NANDs, NORs and NOT) used.

// 2-to-4 Decoder implemented in structural verilog style.
module decoder_2_to_4 (B, A, G, Y0, Y1, Y2, Y3);
input B;
input A;
input G;
output Y0;
output Y1;
output Y2;
output Y3;
wire NOTB;
wire NOTA;

    // Structural verilog style.
NOT u1 (B,NOTB);
NOT u2 (A,NOTA);
AND3 u3 (NOTB,NOTA,G,Y0);
AND3 u4 (NOTB,A,G,Y1);
AND3 u5 (B,NOTA,G,Y2);
AND3 u6 (B,A,G,Y3);

endmodule

`timescale 1 ns / 100 ps

module test_fixture;
reg done;
//  reg [1:0] test_input;   //2 input
reg [2:0] test_input;   //3 input
wire f0, f1, f2, f3;        //Put output wires here

initial
begin
   $dumpfile("decoders.vcd"); // save waveforms in this file
   $dumpvars;                 // saves all waveforms

   // initialize done signal to 0
   done = 1'b0;
/*
//2 Input Test
   // test 00 case
   test_input[1] = 0;
   test_input[0] = 0;

   // wait 5 ns, then test 001 case
   #5 
   test_input[1] = 0;
   test_input[0] = 1;

   // wait another 5 ns, then test 010 case
   #5
   test_input[1] = 1;
   test_input[0] = 0;

   // wait another 5 ns, then test 011 case
   #5
   test_input[1] = 1;
   test_input[0] = 1;

   // Bogus kluge to extend simulation time for better viewing.
   #5 done = 1'b1;

   $finish;       // finished with simulation
end
*/
// 3 input test

   // test 000 case
   test_input[2] = 0;
   test_input[1] = 0;
   test_input[0] = 0;

   // wait 5 ns, then test 001 case
   #5 
   test_input[2] = 0;
   test_input[1] = 0;
   test_input[0] = 1;

   // wait another 5 ns, then test 010 case
   #5
   test_input[2] = 0;
   test_input[1] = 1;
   test_input[0] = 0;

   // wait another 5 ns, then test 011 case
   #5
   test_input[2] = 0;
   test_input[1] = 1;
   test_input[0] = 1;

   // wait another 5 ns, then test 100 case
   #5
   test_input[2] = 1;
   test_input[1] = 0;
   test_input[0] = 0;

   // wait another 5 ns, then test 101 case
   #5
   test_input[2] = 1;
   test_input[1] = 0;
   test_input[0] = 1;

   // wait another 5 ns, then test 110 case
   #5
   test_input[2] = 1;
   test_input[1] = 1;
   test_input[0] = 0;

   // wait another 5 ns, then test 111 case
   #5
   test_input[2] = 1;
   test_input[1] = 1;
   test_input[0] = 1;


// Instantiate circuit
decoder_2_to_4 u0 (test_input[2], test_input[1], test_input[0], f0, f1, f2, f3);
end
endmodule   // test_fixture

The problem is that when I compile I receive the following errors:

Identifier (decoder_2_to_4) not declared
"test.v", 94:

syntax error
"test.v', 94: decoder_2_to_4 u0<-

Does anyone have a clue why I am getting this? I really have no idea what is going on, and a nudge in the right direction would certainly help. Thanks in advance.

Edit: To further confirm the compilation error, the prebuilt_gates file (the one not listed) and Decoders.v (the file containing the 2-to-4 Decoder implementation) both compile together just fine without test.v (the second file posted and the one that is noted by the errors.) Problem is definitely in there somewhere.

Upvotes: 0

Views: 12875

Answers (1)

Greg
Greg

Reputation: 19122

The circuit should not be instantiate inside the initial block.

// Instantiate circuit
decoder_2_to_4 u0 (test_input[2], test_input[1], test_input[0], f0, f1, f2, f3);
end
endmodule   // test_fixture

should be:

end
// Instantiate circuit
decoder_2_to_4 u0 (test_input[2], test_input[1], test_input[0], f0, f1, f2, f3);
endmodule   // test_fixture

modules can only be instantiated inside other modules or generated-blocks (and generate-blocks can only be instantiated inside modules). It is illegal to instantiate module in any other manner such as inside a initial-block or always-block.

Instantiating a module inside an initial, always, task, or function will attempt to treat the module as an variable, of which non exists and give an error.

The actual rule itself is spreed out in IEEE Std 1800-2012 Annex A. Look for all the places module_instantiation is used within Annex A.

Upvotes: 2

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