Reputation: 39
I'm trying to do some projects on Verilog, and I have a problem with constant index errors.
integer k=32;
reg[k-1:0] inputs;
In this code, the Verilog compiler gives me this message:
Expected a constant as index error in Verilog
I must use integer k
in this project. How can I solve this problem?
Upvotes: 1
Views: 609
Reputation: 62236
integer
is a variable type. As the error message states, you need a constant type, such as parameter
:
parameter k=32;
reg[k-1:0] inputs;
Upvotes: 1