CODEWITHSUNDEEP
verilogsystem-verilog
lin ki
lin ki

Reputation: 39

Undeclared identifier in Verliog

I'm doing some projects in Verilog and I got some problems with this part of the code.

'''
parameter OP_mode = 2'b01;

if(OP_mode == 2'b00)
  parameter k=4;
else if(OP_mode == 2'b01)
  parameter k=8;
      .
      .
      .
reg [k-1:0] inputs;

'''

In this case, the compiler gives me the error "Undeclared Identifier: k" How can I solve this error?

Upvotes: 0

Views: 1050

Answers (1)

dave_59
dave_59

Reputation: 42616

You are declaring your parameters inside an unnamed block of code that cannot be referenced from outside (IEEE 1800-2017 SystemVerilog LRM)

27.5 Conditional generate constructs

Generate blocks in conditional generate constructs can be named or unnamed, and they may consist of only one item, which need not be surrounded by begin-end keywords. Even if the begin-end keywords are absent, it is still a generate block, which, like all generate blocks, comprises a separate scope and a new level of hierarchy when it is instantiated.

parameter OP_mode = 2'b01;
if(OP_mode == 2'b00) begin: block
  parameter k=4;
end
else if(OP_mode == 2'b01) begin : block
  parameter k=8;
end
logic [k-1:0] inputs;

A better way is using a function call:

module top;
  
  parameter OP_mode = 2'b01;
  
  function int f_k;
    if(OP_mode == 2'b00)
       return 4;
    else if(OP_mode == 2'b01) 
       return 8;
    return 0;
  endfunction
  
  parameter k = f_k();
  logic [k-1:0] inputs;

Upvotes: 3

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