CODEWITHSUNDEEP
system-veriloguvm
justrajdeep
justrajdeep

Reputation: 913

How to extend from a class present in the scope of a system verilog interface?

I was going through this since some of my UVC use this methodology:

https://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_guidelines/parameterized_interface/

But i want to extend the class in the interface and add/override some more functionality.

But when i tried to override the class, the compiler could not find the class, since it is scoped in the interface.

Any suggestions as to how I can override the class instead of re-implementing all the functions?

Thanks in advance.

Upvotes: 1

Views: 419

Answers (1)

dave_59
dave_59

Reputation: 42623

That is one problem with using this methodology - you can only extend the class from within the interface. But that is no different from using a virtual interface — you cannot extend the interface.

The best thing you could do in put the extended class inside the interface. Use the factory to override the construction of the class.

Upvotes: 2

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