CODEWITHSUNDEEP
verilogclockdivider
user9470713
user9470713

Reputation: 1

Clock divider by 8

I have 1 module for click divider by 2

module divider_by2 ( clk ,rst,out_clk );
    output reg out_clk;
    input clk, rst;

    always @(posedge clk)
    begin
        if (~rst) out_clk <= 1'b0;
        else out_clk <= ~out_clk;   
    end

endmodule

Now I want to reuse this module for making clock divider by 8

module top(clk, rst, out_clk);
    output reg out_clk;
    input clk, rst;

    wire out_clk1;
    wire out_clk2;

    divider_by2 obj1(clk, rst, out_clk1);
    divider_by2 obj2(out_clk1, rst, out_clk2);
    divider_by2 obj3(out_clk2, rst, out_clk);

endmodule

And tb for top module

module divtb ();
    wire out_clk;
    reg clk, rst;

    top topp(clk, rst, out_clk);

    initial begin
      $dumpfile("dd.vcd");
      $dumpvars(0, divtb);

      clk = 0;
      #1 reset = 1;
      #1 reset = 0;

     #125;
     $finish;
    end
   always
    #1 clk = !clk;
 endmodule

Getting error:

d.v:23: reg out_clk; cannot be driven by primitives or continuous assignment.

d.v:23: error: Output port expression must support continuous assignment.

d.v:23: : Port out_clk of divider_by2 is connected to out_clk 2 error(s) during elaboration.

What should I do ?

Upvotes: 0

Views: 1905

Answers (1)

Vlad
Vlad

Reputation: 5902

You have the register in divider_by2 module, so you don't need the register in top module to expose the last divider's output.

Just drop that reg in top module's out_clk output.

Upvotes: 1

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