CODEWITHSUNDEEP
vivado-hls
wahab
wahab

Reputation: 835

Vivado HLS if Condition Synthesis

I want to synthesize the following code in Vivado HLS:

if (x == 1) regA = 1;

When this code is synthesized, the corresponding VHDL block looks something like this:

if (not(x_synth = logic_0)) regA_synth = logic_1

The problem with this code is that regA is assigned logic 1 if x is anything but logic 0 i.e. even if it's U or Z. Is there any other way to rewrite the original if statement, so that it is synthesized in such a way that regA is only assigned logic 1 if x is logic 1?

Upvotes: 0

Views: 896

Answers (1)

Gyzuh
Gyzuh

Reputation: 181

I don't think there is a method to do this. You can perhaps achieve this with experimentation.

I do agree that U and Z values should be propagated through the design to guarantee that they are caught at the output in batch mode simulations, but sadly that is not the case. As these values should not be originating from your C code itself, you can perhaps monitor the inputs to your block. I also don't like the fact that Vivado HLS puts X values on buses between transactions. That makes it harder to spot wires that have multiple sources. Anyway, I would provide your feedback to Xilinx such that they can improve the tool.

Upvotes: 0

Related Questions