StackOverflow Questions for Tag: vivado-hls

physicist1911

Reputation: 103

Bitonic sort: how can I find the top N elements from an array of length K, without doing a full sort - stopping when the top N are found?

algorithmsortingvivado-hlssorting-network

Score: 3

Answers: 2

Florence

Reputation: 59

How to store image in the FPGA for real time video processing?

fpgaxilinxvivadozynqvivado-hls

Score: 0

Answers: 1

atnd

Reputation: 21

Why am I not able to write to/read from custom AXI lite peripheral's registers

vhdlfpgavivadozynqvivado-hls

Score: 2

Answers: 1

Sooora

Reputation: 191

Can we use scanf in the test bench?

hardwarevivado-hls

Score: 0

Answers: 1

zjnyly

Reputation: 365

How to implement pipelined floating point accumulation in II=1 in Vitis/Vivado HLS?

xilinxvivado-hlsvitis

Score: 0

Answers: 1

student

Reputation: 19

Vivado HLS 2018.2 - Unknown option '-disable_start_propagation' in set_directive_dataflow

tclvivadovivado-hls

Score: 0

Answers: 1

agni_ka1

Reputation: 29

Verilog FPGA poor placement for routing between IO pin and BUFG error?

fpgahdlvivadovivado-hls

Score: 0

Answers: 0

JustAnotherMind

Reputation: 1

How can I give HLS directive using Tcl script for all functions to make them combinational?

tclvivado-hls

Score: 0

Answers: 1

Tarick Welling

Reputation: 3265

How to create a trigger signal in vivado HLS

vivadovivado-hls

Score: 0

Answers: 1

136

Reputation: 1207

Vitis HLS Pointer to Pointer is not supported for variable when initializing struct array

cfpgaxilinxregister-transfer-levelvivado-hls

Score: 3

Answers: 1

Sharanesh R

Reputation: 1

Running two functions parallely in Vitis HLS that have different Initiation Intervals?

xilinxvivado-hls

Score: 0

Answers: 1

TylerChang

Reputation: 1

Vitis HLS: pragma Array Partition doesn't work in the sub-function when I set this pragma outside

vivado-hls

Score: 0

Answers: 1

devdc

Reputation: 161

Vitis HLS 2022.2 ERROR: [HLS 200-1715] Encountered problem during source synthesis

xilinxvivado-hls

Score: 0

Answers: 1

User626

Reputation: 3

question regarding limitations on using c instead of c++ on vitis hls

xilinxvivadovivado-hlsvitis-ai

Score: 0

Answers: 1

AKRA

Reputation: 288

HLS : Cellular Automata

c++11fpgaxilinxvivadovivado-hls

Score: -1

Answers: 1

user21095056

Reputation: 1

How to find delay of circuit?

fpgaxilinxvivadovivado-hls

Score: -1

Answers: 1

hdcoe

Reputation: 1

Different resource utilization shows in vivado hls and vivado

cfpgavivadovivado-hls

Score: 0

Answers: 2

Nah

Reputation: 21

MSE giving negative results in High-Level Synthesis

powfixed-pointtest-benchmsevivado-hls

Score: 0

Answers: 1

amur

Reputation: 117

What's the biggest fixed point number that can be expressed in 8 bits?

bitvivadofixed-pointvivado-hls

Score: 0

Answers: 1

Тёма Ершов

Reputation: 1

How can I create a grayscale image for Vivado HLS?

c++fpgahdlvivadovivado-hls

Score: -3

Answers: 1

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StackOverflow Questions for Tag: vivado-hls

Bitonic sort: how can I find the top N elements from an array of length K, without doing a full sort - stopping when the top N are found?

How to store image in the FPGA for real time video processing?

Why am I not able to write to/read from custom AXI lite peripheral&#39;s registers

Can we use scanf in the test bench?

How to implement pipelined floating point accumulation in II=1 in Vitis/Vivado HLS?

Vivado HLS 2018.2 - Unknown option &#39;-disable_start_propagation&#39; in set_directive_dataflow

Verilog FPGA poor placement for routing between IO pin and BUFG error?

How can I give HLS directive using Tcl script for all functions to make them combinational?

How to create a trigger signal in vivado HLS

Vitis HLS Pointer to Pointer is not supported for variable when initializing struct array

Running two functions parallely in Vitis HLS that have different Initiation Intervals?

Vitis HLS: pragma Array Partition doesn&#39;t work in the sub-function when I set this pragma outside

Vitis HLS 2022.2 ERROR: [HLS 200-1715] Encountered problem during source synthesis

question regarding limitations on using c instead of c++ on vitis hls

HLS : Cellular Automata

How to find delay of circuit?

Different resource utilization shows in vivado hls and vivado

MSE giving negative results in High-Level Synthesis

What&#39;s the biggest fixed point number that can be expressed in 8 bits?

How can I create a grayscale image for Vivado HLS?

Why am I not able to write to/read from custom AXI lite peripheral's registers

Vivado HLS 2018.2 - Unknown option '-disable_start_propagation' in set_directive_dataflow

Vitis HLS: pragma Array Partition doesn't work in the sub-function when I set this pragma outside

What's the biggest fixed point number that can be expressed in 8 bits?