CODEWITHSUNDEEP
vhdl
Lavair
Lavair

Reputation: 936

How do I extract a single bit out of a std_logic_vector and convert it to an integer?

I am struggling with type conversion in vhdl. I am pretty new to vhdl and apologize, if this is a really stupid question. But what i want to do is, i want to go through the input vector and add all bits together to form an integer. For example "11001010" shall result in 4 (or "100"). And "11101010" would result for example in 6 (or "110"). How can i achieve that?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity xyz is
    port(
        input: in std_logic_vector(7 downto 0);
        output: out std_logic_vector(7 downto 0)
    );
end entity;

architecture behaviour of xyz is
    signal temp : integer := 0;
begin
    evaluate_input :process is
    begin
        for i in input'left downto input'right loop
            temp <= temp + to_integer(unsigned(input(i)));
        end loop;
    wait;
    end process;

    stop_simulation :process is
    begin
        wait for 100 ns; --run the simulation for this duration
        assert false
            report "simulation ended"
            severity failure;
    end process;
end xyz;

Upvotes: 1

Views: 3620

Answers (1)

Paebbels
Paebbels

Reputation: 16213

Don't think to complicated. You want to calculate the hamming weight.

for i in input'range loop
  temp <= temp + (1 when (input(i) = '1') else 0);
end loop;

Or with your proposed way:

for i in input'range loop
  temp <= temp + to_integer(unsigned(input(i downto i)));
end loop;

unsigned(...) needs an array of std_logic_vector. By using just i, you get a single std_logic. Whereas, i downto i creates another std_logic_vector of length 1, which can be used in unsigned.

Upvotes: 2

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