CODEWITHSUNDEEP
verilog
Ranju
Ranju

Reputation: 76

Unexpected result of verilog dflipflop code

For below verilog dff example output is shown at last(only shown first two lines). I am not able to understand why the always block is executing at time zero whereas I have written always@(posedge clk). posedge clk is not happening at time zero. Can you help me to understand the output? 

module main;
reg d,clk;
wire q;

always #5 clk++;
always #10 d++;

dff dff(d,clk,q);  

initial 
begin
d = 1;
clk = 1;
$monitor("time = %d d = %d clk = %d q = %d",$time,d,clk,q);
#50 $finish ;
end
endmodule

module dff(input wire d,clk, output reg q);
always @(posedge clk)
begin
q = d;
$display("time = %d inside module dff",$time);
end
endmodule

Output is
time =                    0 inside module dff
time =                    0 d = 1 clk = 1 q = 1
...

Upvotes: 0

Views: 113

Answers (1)

sharvil111
sharvil111

Reputation: 4381

Use non-blocking assignments (q<=d;) while coding sequential logic. The non-blocking assignments will assign the LHS in NBA region and we can observe a clock delay between the LHS and RHS.

Refer to this paper for more information on non-blocking assignments usage.

As far as always block executing at time-0, there is a clk transition from x to 1 at time-0 (from initial block). As a result, the simulator counts it as a positive edge. Note that the default value of reg is x.

We can make different types of clock generators in Verilog/SV as per requirement. Refer to Cummings paper for examples on different types of clock generators.

Upvotes: 3

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