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vhdlmodelsim
Matthieu
Matthieu

Reputation: 21

How to modify initialization done by modelsim?

My question is related to the initialization done by modelsim. I want to use integer in a particular range (range 0 to 511 for example). Here is the declaration in VHDL: 

signal cnt : natural range 0 to 511;

If I do not initialize this signal (in a reset for example), modelsim will assign the leftmost value by default. For my signal, it would be 0.

My problem is I would like to force modelsim to initialize its value in simulation to 'U' or 'X' instead of the leftmost value, is it possible ?

Upvotes: 2

Views: 1577

Answers (1)

Renaud Pacalet
Renaud Pacalet

Reputation: 28935

Signals can be given an initialization value at declaration:

signal foo: foo_type := foo_type_value;

Note the := assignment operator which may look a bit counter-intuitive for a signal.

But no, it is not possible to assign 'U' or 'X' to a signal which type is natural because they are not natural values. What you can do, instead, is decide that value 512 is the equivalent of U for your signal and assign it at declaration time:

signal cnt : natural range 0 to 512 := 512;

As this extra value is not supposed to be used after initialization you could (should) add a concurrent assertion to detect unwanted situations:

assert cnt /= 512 report "Ooops! cnt=512" severity warning;

Another option is to use ieee.numeric_std.unsigned instead of natural:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
signal cnt : unsigned(8 downto 0) := (others => 'U');

But before using this, be sure you understand the differences. For instance, if you try to decrement your natural cnt while its value is 0 you will get an error while with the unsigned version cnt will silently wrap to "111111111".

Upvotes: 2

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