CODEWITHSUNDEEP
chiselregister-transfer-level
Amin Habibi
Amin Habibi

Reputation: 31

passing arguments to verilator backend in chisel

i have wrote a simple PeekPokeTester testbench in chisel and it compiles and run successfully using verilator backend.
but now i want to pass some flags to verilator backend. in driver options there is a "--more-vcs-flags" option but there is not a similar thing for verilator. is there any way to change verilator flags or CFLAGS? to be more specific i want to simulate xilinx primitives as blackbox in chisel and i have to add something like "-y $VIVADO_INSTALL_DIR/data/verilog/src/unisims" to verilator compilation command
thanks

Upvotes: 3

Views: 687

Answers (1)

FabienM
FabienM

Reputation: 3761

There is an issue open for this subject on project : https://github.com/freechipsproject/chisel-testers/issues/148

Upvotes: 2

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