CODEWITHSUNDEEP
optimizationvhdl
Bort
Bort

Reputation: 133

When must/should I declare a variable with the range keyword in VHDL?

I am new to VHDL and have perhaps a basic question, but here goes:

When declaring a variable, say an integer, what is the benefit of

variable count_baud  : integer range 0 to clk_freq/baud_rate - 1 := 0;

vs.

variable count_baud  : integer := 0;

Is the point of using range (only) to limit the size of the synthesized real estate in the CPLD/FPGA?

Upvotes: 1

Views: 227

Answers (1)

Renaud Pacalet
Renaud Pacalet

Reputation: 29167

There are two very good reasons:

  1. Debugging. If you know that your integer shall stay in the [min..max] range, tell it to the simulator with a proper range declaration. In case there is a bug in your code and you try to assign an out-of-range value, the simulator will let you know with a very useful message. While if you just declared an integer the error could happen long after the bogus assignment.

  2. Synthesis quality. A logic synthesizer, by default, will allocate 32 bits for an integer. Depending on the surrounding it may discover that less bits are sufficient... or not. So, telling the synthesizer what the real range is frequently saves hardware, power and increases the final performance (speed), especially if the real range can be represented on much less than 32 bits.

Upvotes: 3

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