CODEWITHSUNDEEP
makefile
Gautitho
Gautitho

Reputation: 623

Makefile : include in loop / loop outside targets

In my makefile I want to include some other makefile depending on a variable in a for loop, Is it possible.

Top Makefile :

CC          = gcc
CFLAGS      = -O0 -g3 -W -Wall -pedantic
LDFLAGS     =

DEFINES     =
PROJECT     = proj

INCLUDES    =
SOURCES     =

TEMP_PATH   := $(PROJECT)
include $(TEMP_PATH)/Makefile

$(for blocks in $(BLOCKS); do \
    include $$(blocks)/Makefile; \
done)

all : $(PROJECT).exe

$(PROJECT).exe :
    $(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) $(INCLUDES) $(SOURCES) -o $@

clean :
    rm -rf *.exe

proj/Makefile : 

CC          =   gcc
CFLAGS      = -O0 -g3 -W -Wall -pedantic
LDFLAGS     = 

DEFINES     =  

BLOCKS      := std_communication

INCLUDES    := $(INCLUDES) -I $(TEMP_PATH)/Utils
INCLUDES    := $(INCLUDES) -I $(TEMP_PATH)/Communication

SOURCES     := $(SOURCES) $(wildcard $(TEMP_PATH)/Utils/*.c)
SOURCES     := $(SOURCES) $(wildcard $(TEMP_PATH)/Communication/*.c)
SOURCES     := $(SOURCES) $(wildcard $(TEMP_PATH)/main.c)

The for loop syntax seems to be wrong outside of loop.

Upvotes: 0

Views: 275

Answers (1)

MadScientist
MadScientist

Reputation: 100876

You cannot write it like that, but you can just write:

include $(addsuffix /Makefile,$(BLOCKS))

Upvotes: 2

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