CODEWITHSUNDEEP
chisel
user3567895
user3567895

Reputation: 668

Vector of RegEnable

Looking for an example/advice on how to use RegEnable as vector. Also I want to control the inputs & enable signals to be a function of the register index in the Vector.

So first, how do I declare Vector of RegEnable(), and second how to iterate over it and connect the input & enable. In the RegEnable() case the declaration and the connection are made in the same statement. Something like:

for (j <- 0 until len) {
    val pipe(j) = RegEnable(in(j),en(j))    
}

The above code doesn't compile. Also in & en are vectors or bit selection

Upvotes: 3

Views: 540

Answers (1)

seldridge
seldridge

Reputation: 2874

For this type of thing, it's likely much easier to use RegEnable to construct a Seq[T <: Data] and then construct a Vec out of that. The Vec object has two main apply methods: a varargs one and a seq. For your own reference, take a look at the Chisel Vec object API documentation.

The following full example builds, but the relevant part is the val pipe and val pipe2 lines. You can do this with either a map or a for/yield.

import chisel3._

import chisel3.util.RegEnable
import chisel3.iotesters
import chisel3.experimental.MultiIOModule

class Example(len: Int) extends MultiIOModule {
  val in = Seq.fill(len)(IO(Input(UInt(1.W))))
  val en = Seq.fill(len)(IO(Input(Bool())))

  val mySeq: Seq[Data] = (0 until len).map( j => RegEnable(in(j), en(j)) )
  val pipe = Vec(mySeq)

  val mySeq2: Seq[Data] = for (j <- 0 until len) yield ( RegEnable(in(j), en(j)) )
  val pipe2 = Vec(mySeq2)
}

Upvotes: 5

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