CODEWITHSUNDEEP
functionvhdlalias
Thomas Ameseder
Thomas Ameseder

Reputation: 33

How can I write an alias in VHDL (post-87; i.e. 93, 2008) for a function call?

I have a function call to ease signal conversion that would otherwise repeat throughout the source code.

Now, as a further optimization, I want to make the rather elaborate function calls (with two parameters that are mostly the same) more readable and easier to write using an alias.

VHDL standards after '87 allow aliases for non-data objects, e.g. subprogram calls. Looking for a solution I learned that functions require a signature as part of the alias declaration. Yet, I could not find documentation that helped me declare an alias for my function that works with Synopsys VCS.

function discard_elem (
  signal discard_vector : in std_ulogic_vector(63 downto 0);
  signal id             : in std_ulogic_vector(5 downto 0))
  return std_ulogic is
begin
  return discard_vector(to_integer(unsigned(id)));
end discard_elem;

alias discard_current_elem is 
  discard_elem(discard_vector_i, interface_i.id) [ return std_ulogic ];

VCS reports the following error, then quits with a segmentation fault:

Error-[ANL-ALIAS-BADSIGNAT] Bad signature in alias declaration
                                                                          ^
  No subprogram or enumeration literal matches the signature of the alias 
  declaration DISCARD_ELEM.
  Please verify that the signature matches the parameter and result type 
  profile of exactly one of the subprograms or enumeration literals.

Is the alias definition wrong or is this a tool issue?

Upvotes: 3

Views: 1099

Answers (2)

Tricky
Tricky

Reputation: 4461

Aliases really are just that, a renaming of the same function, with the same parameters (as posted by @Matthew Taylor). You cannot change the signature, so an alias still has to be called with the same parameters as the original function.

What you are suggesting is a wrapper/helper function/procedure, that uses the local scope to access local signals/variables:

signal discard_vector_i : std_ulogic_vector(63 downto 0);
signal interface_id     : some_record_type;

impure function discard_current_elem return std_ulogc is 
begin
  return discard_elem(discard_vector_i, interface_i.id); -- scope used to access these parameters
end function;

Upvotes: 2

Matthew
Matthew

Reputation: 13967

I think you are confusing an alias with a macro (in Verilog and other languages). You can't include the actuals (the function arguments) in the alias. So, you can do this:

alias discard_current_elem is discard_elem[std_ulogic_vector, std_ulogic_vector return std_ulogic];

but I don't think that is what you were hoping for.

https://www.edaplayground.com/x/5QS_

Upvotes: 3

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