CODEWITHSUNDEEP
makefile
irssquare
irssquare

Reputation: 93

Makefile wildcard and variable expansion

I have this Makefile (abbreviated):

COMPILE                  = armcc
LINK                     = armlink
SRCDIR := ./src1 \
          ./src2

INCLUDES := -I ./inc 
CSRC := $(wildcard $(SRCDIR)/*.c)
# CSRC := ./src1/*.c ./src2/*.c
OBJS := $(CSRC:.c=.o)

.PHONY: clean

clean:
    @echo "Clean Finished"

%.o: %.c
    @echo Compiling $<
    @$(COMPILE) $(INCLUDES) $< -o $@

mktest: $(OBJS) Makefile
    @echo $(CSRC)
    @echo $(OBJS)
    @echo building mktest
    @$(LINK) -o mktest.axf

When I run it the wildcard only expanded for the last entry in the SRCDIR variable, which is ./src2. The output shown below.

c:> make mktest
./src1 ./src2/file2.c
./src1 ./src2/file2.o
building mktest

If I replace the line where CSRC defined, with the line below it. It works fine, and the output shown below.

c:> make mktest
./src1/*.c ./src2/*.c
./src1/*.o ./src2/*.o
building mktest

This is OK if I only have a few sub-directories I want to include. But if I want to include more, the Makefile will become ugly. Am I not using the wildcard function properly here?

Upvotes: 6

Views: 4875

Answers (1)

Ondrej K.
Ondrej K.

Reputation: 9664

What you would need your CSRC definition to be is:

CSRC:= $(foreach dir,$(SRCDIR),$(wildcard $(dir)/*))

If you look at the documentation:

$(wildcard pattern…)

This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match one of the given file name patterns…

This means your original line actually reads as:

CSRC := $(wildcard src1/ src2/*.c)

That is files whose names are matching against src1/ or src2/*.c.

Upvotes: 8

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