CODEWITHSUNDEEP
verilog
Brahadeesh
Brahadeesh

Reputation: 2255

Verilog net to reg assignment

I have an input port from_LS(511:0). This is declared as wire in my module. I am assigning this to a set of 32 registers ilb(0:31), each of which are 1 nits long. I was trying to use the for loop to do this. 

 integer i;
 genvar j;
 initial
  begin
    count1 = 0;
    count2=0;
    flush_ctrl=0;
    buffer_bit=0;
    a=(hmic_ctrl[1]) + (hmic_ctrl[2]*2) + (hmic_ctrl[3]*4);
    //assigning data from LS to ilb

        for (i=0;i<=31;i=i+1)
          ilb[i]=from_LS[511-(16*i) : 511-(16*(i-1))];

    ilb[0]= from_LS[511:496];
    ilb[1]= from_LS[495:480];
    ilb[2]= from_LS[479:464];
    ilb[3]= from_LS[463:448];
    ilb[4]= from_LS[447:432];
    ilb[5]= from_LS[431:416];
    ilb[6]= from_LS[415:400];
    ilb[7]= from_LS[399:384];
    ilb[8]= from_LS[383:368];
    ilb[9]= from_LS[367:352];
    ilb[10]= from_LS[351:336];
    ilb[11]= from_LS[335:320];
    ilb[12]= from_LS[319:304];
    ilb[13]= from_LS[303:288];
    ilb[14]= from_LS[287:272];
    ilb[15]= from_LS[271:256];
    ilb[16]= from_LS[255:240];
    ilb[17]= from_LS[239:224];
    ilb[18]= from_LS[223:208];
    ilb[19]= from_LS[207:192];
    ilb[20]= from_LS[191:176];
    ilb[21]= from_LS[175:160];
    ilb[22]= from_LS[159:144];
    ilb[23]= from_LS[143:128];
    ilb[24]= from_LS[127:112];
    ilb[25]= from_LS[111:96];
    ilb[26]= from_LS[95:80];
    ilb[27]= from_LS[79:64];
    ilb[28]= from_LS[63:48];
    ilb[29]= from_LS[47:32];
    ilb[30]= from_LS[31:16];
    ilb[31]= from_LS[15:0];
    pctr(
     .clk(clk),
     .reset(0),
     .offset(branch_ctrl[13:1]),
     .mux_select(branch_ctrl[0]),
     .pc1(pc)
   );
  end

I was getting the error that I should not use a variable index. The error is :

# ** Error: C:/Modeltech_pe_edu_10.0/examples/COMP ARC/inst_line_buf.v(55): Range must be bounded by constant expressions.

So i wrote down the following:

ilb[0]= from_LS[511:496];
ilb[1]= from_LS[495:480];
ilb[2]= from_LS[479:464];
....
ilb[31]= from_LS[15:0];

But i guess there must be a better way to do this. Could anyone tell me how?

Upvotes: 1

Views: 1278

Answers (2)

flolo
flolo

Reputation: 15496

The orginal verilog doesnt allow this kind of expression as it wanted to assure that the width is always right (it is, but in earlier times compilers werent as good :-).

Verilog 2001 offers some solution with +: you can specify the width e.g. from_LS[ 511-(16*i) +:16 ] in your loop.

EDIT: Another solution would be to put another loop inside, which copies 16 bits bit by bit.

Upvotes: 2

Ben Jackson
Ben Jackson

Reputation: 93770

You should include more code (at least up to the always block containing that loop for the sensitivity list) and the exact error you're getting.

Does it work if you change integer i to genvar i and wrap the for in generate and endgenerate?

Upvotes: 1

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