CODEWITHSUNDEEP
assemblymemorycpu-architecture
Kuldeep Sarma
Kuldeep Sarma

Reputation: 43

Why is program counter incremented by 1 if memory organised as word and by 2 in case of bytes?

If in a computer an instruction is of 16 bits and if memory is organized as 16-bits words, then the address of the next instruction is evaluated by adding one in the address of the current instruction. In case, the memory is organized as bytes, which can be addressed individually, then we need to add two in the current instruction address to get the address of the next instruction to be executed in sequence. Why is it so?? Please explain this concept. I am new to computer organisation and assembly language programming so any help is appreciated. Thanks.

Upvotes: 4

Views: 5092

Answers (2)

Martin Rosenau
Martin Rosenau

Reputation: 18493

Your question does not say what architecture you are referring to.

Talking about designs that do not allow instructions to be aligned to bytes, the behavior you describe differs from CPU to CPU!

First we look at the meaning of the "address" on 8-bit CPUs. On such CPUs the address is increased by 1 when going from one byte to the next byte in memory:

Address   Meaning
0         1st byte in memory
1         2nd byte in memory
2         3rd byte in memory
3         4th byte in memory
4         5th byte in memory
...

The 68000 uses a similar addressing like 8-bit CPUs. However, the memory is actually organized in 16-bit units and instructions must start at an even address and are a multiple of 16 bits long. Therefore the program counter always contains an even value. It will increase by 2 or a multiple of 2 during each instruction.

(Using odd addresses is only allowed for byte-wise memory access (read/write) which will actually perform a 16-bit memory access in the background.)

For the TMS9900 (a 16-bit CPU) the address is increasing by 1 for 16 bits; the bytes in between can be accessed but the addresses are formed by adding 0x8000:

Address   Meaning
0         1st byte in memory
0x8000    2nd byte in memory
1         3rd byte in memory
0x8001    4th byte in memory
2         5th byte in memory
...

The program counter may contain an odd or an even value here, but not a value above 0x7FFF because this would refer to a byte which is not 16-bit aligned. Of course, the program counter will increase by 1 when the instruction is 16 bits long.

The TMS320 does not allow addressing odd bytes:

Address       Meaning
0             1st + 2nd byte in memory
not possible  2nd + 3rd byte in memory
1             3rd + 4th byte in memory
2             5th + 6th byte in memory
...

In this design the program counter will also increase by 1 when the instruction is 16 bits long.

The LittleMIPS (or similar; I don't remember the correct name) design is a reduced MIPS CPU intended for students to learn microchip design. It allows only 32-bit memory access and only 4-aligned addresses:

Address       Meaning
0             1st to 4th byte in memory
1             address does not exist
2             address does not exist
3             address does not exist
4             5th to 8th byte in memory
5             address does not exist
...

On this design the program counter will always contain a multiple of 4. Because each instruction is exactly 4 bytes long, the program counter will increase by 4 during an instruction.

Upvotes: 5

Peter Cordes
Peter Cordes

Reputation: 364068

If the smallest addressable unit is 2 bytes, then adjacent 2-byte instruction words are only 1 address apart.

The whole point of word-addressable memory is to avoid wasting an address bit on byte-within-word in a system that can't do byte loads/stores in the first place.

Upvotes: 3

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