CODEWITHSUNDEEP
cmakefilecompilation
Ursa Major
Ursa Major

Reputation: 901

Not able to include folder for C compilation

Everything compile if the C is in outer folder, but when lib.c is in [lib] folder, it gives an error: make: *** No rule to make target 'obj/lib.o', needed by 'run'. Stop.

How should the makefile be corrected to make sure the compilation is successful?
What is the correct way to emend the makefile?

The tree is such:

 ├── inc
 │   └── main.h
 ├── lib
 │   └── lib.c
 ├── main.c
 ├── main_functions.sh
 ├── Makefile
 └── test_usages.c

The makefile:

# IDIR =../include \
This is a makefile \

IDIR =./inc
CC=gcc

ODIR=obj
# LIB_SRC_DIR =./lib
LDIR =./lib 
CFLAGS=-I $(IDIR) $(LDIR)   ## added $(LDIR)

# header files required
_DEPS = *.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

_DEP_LIB = *.c                                  ##
DEPS_LIB = $(patsubst %,$(LDIR)/%,$(_DEP_LIB))  ##

_OBJ = lib.o main.o test_usages.o 
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

 $(ODIR)/%.o: %.c $(DEPS) $(DEPS_LIB)       ## added $(DEPS_LIB)
     $(CC) -c -o $@ $< $(CFLAGS) 

 #%.o: %.c
 #      $(CC) $(CFLAGS) $(INCLUDES) -c $(input) -o $(output)

 # make commands options: make <options>, e.g. make hello_make  
 # executable name
 hello_make: $(OBJ)
     gcc -o $@ $^ $(CFLAGS)

 run: $(OBJ)
     gcc -o $@ $^ $(CFLAGS)
     echo "=========================================================="
     ./run
     echo "=========================================================="

 .PHONY: clean

 clean:
     echo "cleaning ...." $(ODIR)/*.o
     rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~ ./*.exe

Thanks in advance for the advice.

Upvotes: 0

Views: 78

Answers (1)

the busybee
the busybee

Reputation: 12673

There are some quirks in your Makefile, but here is how I got it to work:

  1. Remove trailing blank in the line LDIR =./lib
  2. Insert VPATH=$(LDIR) at some convenient place

Now make -n run shows (but doesn't run) all expected command lines:

gcc -c -o obj/lib.o ./lib/lib.c -I ./inc ./lib
gcc -c -o obj/main.o main.c -I ./inc ./lib
gcc -c -o obj/test_usages.o test_usages.c -I ./inc ./lib
gcc -o run obj/lib.o obj/main.o obj/test_usages.o -I ./inc ./lib
echo "=========================================================="
./run
echo "=========================================================="

BTW, you could use these options to debug your Makefile:

make -npr run print all variables, rules and so on, but not the built-ins.

make -nd run print all decisions, a lot of them.

Upvotes: 1

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