CODEWITHSUNDEEP
assemblycpucpu-architecture
Stanley Aloh
Stanley Aloh

Reputation: 437

Simulating data movement while executing assembly instructions using Generic CPU diagram

Image of cpu diagram

I don't if here is the right category for my question. I was giving an assignment to simulate the data movement of this three assembly instruction on an ARM cpu diagram above. 

1. mov  r3,r1

2. ldr  r5,[lr]

3. stmfd   sp!,{r4,r5,r6,lr}

of course I know what this instruction do but I have not been able to find any resource that explain in details about the in built flow in a CPU make this instruction work. So I am looking out for any reference or any explanation about how the CPU make this instruction happen using the cpu diagram above.

Upvotes: 0

Views: 143

Answers (1)

Jester
Jester

Reputation: 58762

"this instruction" - which one? You showed three. Also, if you know what each does, why can't you follow it on the diagram?

Anyway, let's take the first one, the mov r3,r1. It's logical to start from the box called "program counter". Going through the multiplexer that places the current instruction fetch address onto the address bus. The memory subsystem then replies with the instruction word on the data bus. That goes through the "instruction reg" into the "instruction decoder" which then drives the control signals for the execution of the instruction. First it tells the "register file" to place the source register r1 into the output multiplexer from which it goes into the ALU that is programmed for a no operation because this is just a simple copy instruction (mov). The unchanged value goes through the "output register" to the data bus. The instruction decoder then tells the top right multiplexer to take that and forward it to the register file storing it into the destination register r3.

Upvotes: 1

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